General Shift Register

Monday, September 25th, 2017 - Digital

Basically, we can make the shift registerusing a variety of flip-flop, such as flip-flops RS, JK, D, and T. Importantly, it is in synchronous sequential circuits, which means that the output state is determined by the input, the output current (current output) and each output is changed at the same time (the connotation of synchronous) to guarantee data integrity.

In the picture below looks a series of generic shift register, which is made by using 7 flip-flop D. Four first flip-flop (from left) are connected with preset X4, X3, X2, and X1, which is intended as input data. Preset input this data can only be used if the preset enable value 1.

General Circuit For Shift Register

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If the first four flip-flop (from left) serves to receive and represent data, then the last three flip-flop serves as a buffer reservoir, to open up the possibility of cascading. If the initial conditions X4, X3, X2, and X1 respectively value 1, 0, 0, and 0 and presets enable is 1, then the circuit get input valued at 1000. When in this state in the circuit given a ticking clock, there will be a shift to the right data, resulting in the output value of 0100 (000), with the numbers in parentheses are the contents of the buffer. On the next clock ticking, the output will be 0010 (000), and so on. Examples of commands that can be used to perform this function are: <opcode data,n> where n is the number of shifts required and will become a benchmark calculation of this rate clock provided to the circuit.

Of concern here, relates to a series of Shift Register above, is that to shift the data to the right as much as two steps (identical division with 22 required two clock ticking. Means, to perform data shifts to the right as much as three steps ( identical division by 23) required three clock rate. It is also of concern is that the circuit above can only make the process of shifting to the right (identical division by 2n) and can not shift to the left (identical to multiplication by 2n). Functions latter can be met by increasing the number of components that can alter the flow of data shift.

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